Pipelined data processors are generally required to process exceptions as well as normal instructions. A known method of detecting exceptions during data processing is through the use of dedicated logic, such as a programmable logic array (PLA). For example, a common exception that is detected through the use of a PLA is an illegal operation code (opcode). The illegal opcode PLA receives and decodes the instruction opcode to determine whether a legal instruction opcode has been received. If the illegal opcode PLA determines that the instruction opcode is not a legal instruction opcode, the illegal opcode PLA provides information to an entry Read Only Memory (ROM) to process an illegal instruction operation. A problem with providing dedicated logic, such as an illegal opcode PLA, for the purpose of detecting a predetermined exception is the additional area required to implement the dedicated logic. In addition, a problem which may be associated with dedicated logic used to detect an exception is additional data processing time necessary for the illegal opcode PLA to detect an exception. The additional data processing time translates into degraded performance of a pipelined data processor. Therefore, it is preferred to detect exceptions associated with the instruction opcode within a pipelined data processor with a minimal increase in both logic and data processing time.